Custom Silicon 

Epic Semi’s cutting-edge Spec-to-Silicon prowess, paired with our sophisticated design methodologies across state-of-the-art 3nm, 5nm, 7nm, and 12nm foundry processes, as well as 2.5D packaging technology, empowers the creation of innovative designs for Artificial Intelligence (AI), Hyperscale Data Centers, Storage, Data Networking, and High-Performance Computing (HPC)

With our comprehensive proficiency covering the entire spectrum from design to manufacturing of domain-optimized SOCs, Epic Semi stands uniquely positioned to deliver premium custom silicon solutions in advanced nodes, reaching down to 3nm

Front-End Design, Integration, and Verification

Epic Semi possesses the expertise to actively engage during the architecture phase and has a proven track record of delivering numerous customizable subsystems and complete SOCs tailored for AI-enabled applications.

Our capabilities encompass:

  • SOC Micro-architecture
  • RTL Design and Synthesis
  • SOC IP Integration
  • Design Verification
  • FPGA Prototyping

IP Development and Integration

By leveraging our internally developed, highly distinctive IP alongside enduring partnerships with leading IP ecosystem providers, Epic Semi has seamlessly integrated numerous IP components into intricate domain-specific SOCs tailored for datacenter, storage, networking, and AI-enabled applications.

Some notable examples include:

  • Integration of up to 128G SerDes with 256 lanes
  • Support for PCIe Gen5/CXL, HBM, and LPDDR/DDR
  • Die-to-Die IP for chiplets
  • Incorporation of RISC-V and Arm processors

Physical Design

The expertise of Epic Semi’s Physical Design Methodologies team has successfully executed intricate chip tape-outs across a range of process nodes, including the cutting-edge 3nm, catering to high-performance applications in AI, Hyperscale Data Center Computing, Data Networking, Storage, and High-Performance Computing (HPC).

Key Design Features:

    • Large Die-Sizes: Exceeding 400mm2
    • Abundant embedded memory
    • High-Speed Interfaces: Supporting 112G SerDes, HBM3, Die-to-Die (D2D), and PCIe Gen6/CXL 3.0

Wafer Manufacturing

We collaborate with premier foundries, providing a diverse array of processes that encompass cutting-edge technologies like 3nm, 5nm, 7nm, 12nm, and 16nm for high-performance logic, as well as more established nodes tailored for analog or mixed-signal applications.

Epic Semi boasts a longstanding membership in TSMC’s prestigious Value Chain Aggregator (VCA) program

Advanced Packaging Solutions

At Epic Semi, we offer end-to-end solutions, from meticulous package selection to comprehensive design and development, all the way to high-volume manufacturing. We recognize the critical significance of choosing the right packaging solution to align with the technical intricacies and cost parameters of each design.

In our commitment to chiplet innovation, Epic Semi is spearheading the advancement in advanced packaging technologies. We are actively involved in multiple initiatives leveraging cutting-edge 2.5D packaging technologies, including TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) and Integrated Fan-Out on Substrate (InFO_oS)