Epic Semi’s cutting-edge IP and custom silicon proficiency form the cornerstone of prebuilt connectivity chiplets. This innovative and adaptable strategy not only offers cost-effectiveness but also enhances connectivity with higher bandwidth and lower power consumption compared to conventional infrastructure solutions. Leveraging advanced package technologies enables intelligent integration of diverse chip functions through die stacking on a universal substrate

Employing the N-1 (or even N-2) process for the IO chiplet can further amplify savings and accelerate time to market by breaking down the SOC into smaller, more efficient building blocks

The Benefits of Chiplets

Chiplets offer a compelling solution by reducing the overall die cost, albeit requiring more intricate packaging and manufacturing processes. They prove to be particularly advantageous for large dies with minimal redundancy, facilitating favorable heterogeneous integrations of application-specific chiplets

As next-generation processes emerge, the cost benefits are poised to amplify further, with potential savings of up to 35% compared to larger die configurations

IO Chiplets

Reconfigurable ZeusCORE100 SerDes IO with integrated protocol controllers, security IP and AresCORE (that is, D2D-UCIe) IP that enables up to 1.6T of throughput at MR, XLR, and PCIe/CXL reaches


    • Medium Reach Optical Driver Chiplet
    • Extra Long Reach Ethernet Chiplet
    • Combo PCIe/CXL/Ethernet Chiplet
    • 1.6T high speed IO Chiplet

Accelerator Chiplets

High performance, Arm® or RISC-V-based accelerator chiplets—enables data acceleration through Arm or RISC-V multi-core accelerator SOCs





    Memory Chiplets

    Low Latency, high speed DDR5 and memory controller; includes multi-core CPU with L1 and L2 caches