StarLink-500 IP

StarLink-500 is interconnect fabric IP with cache coherence support, supporting the construction of multi-cores and SoC to provide cache coherence NoC: connecting multiple CPU clusters, IO devices, and DDR, and maintaining cache coherence within the SoC.

Design Specification:

  • Support multiple Fully Coherent Master (FCM)ports
  • Support multiple CPU core/cluster configuration
  • Support Component Aggregation Layer (CAL)
  • Support multiple Coherent IO (CIO) ports
  • Frequency: 1.2 Ghz@12nm (Reference)
  • Cache Size: Typical 4 MB (Configurable)
  • Bus Width: 256 Bit (Configurable)
  • High bandwidth, low power consumption, low latency


High Performance:

  • Provides Last Level Cache (LLC), offers Snoop Filter, and improves the efficiency of coherence maintenance modules, and memory hierarchy performance.

Efficient Data Exchange

  • Supports CPU and IO device sharing of LLC, simplifying CPU and IO data exchange and improving performance.

Low Power Consumption

  • Supports LLC way shutdown, cache retention, and other low-power technologies.

High Reliability

  • Snoop Filter and LLC support SEC-DED (Single Error Correction Double Error Detection).

Control Interface Support (CFG & MMIO)

  • CPU configuration of IO devices and on-chip SRAM reading; IO device access and configuration of on-chip interconnect coherence.